ECL-to-CMOS voltage level converters are used in digital design in order to allow a CMOS circuit to input data from an ECL circuit. Since the voltages corresponding to high and low logic levels are different for ECL and CMOS, the ECL input voltage must be shifted to a level which will be recognized by the CMOS. It is important for speed and noise margin considerations that the "trip point" of the CMOS, i.e., the voltage at which CMOS distinguishes between high and low logic levels, be centered with the transition between high and low ECL logic levels after the ECL voltage is shifted.
Prior art ECL-to-CMOS level shifters have the disadvantage of being slow, mainly due to the use of a CMOS current mirror differential pair used to pass signals from the ECL circuit to the CMOS circuit. Since speed is a primary advantage of ECL devices, the slowness of the voltage level shifter is a serious problem.
Therefore, a need has arisen in the industry to provide a ECL-to-CMOS level shifter having high speed and being compatible in a ECL-BiCMOS integrated circuit.